1. Technological Field
The present disclosure relates to improvements in or relating to electrostatic discharge protection, and is more particularly concerned with providing such protection in fin-based field effect transistor technology.
2. Description of the Related Technology
Electrostatic discharge (ESD) protection in fin-based FET (finFET) technology is known to result in more area consumption than in a planar technology because the shallow trench isolation (STI) oxide in between the fins is essentially not used. This increase in required area for ESD protection results in an increased manufacturing cost for integrated circuits (ICs) using finFET technologies.
U.S. Pat. No. 7,141,484 discloses a method of forming an ESD device which includes forming a first and a second semiconductor fin over a substrate and adjacent to one other, epitaxially growing a semiconductor material on the first and the second semiconductor fins so that a first portion of the semiconductor material grown from the first semiconductor fin joins a second portion of the semiconductor material grown from the second semiconductor fin, and implanting different semiconductor materials at a first end portion and a second end portion of the semiconductor material on the first and the second semiconductor fins to form respective first and second implant regions. A p-n junction is formed between the first end and the second end of the semiconductor material, the p-n junction forming a junction of an ESD diode, or a junction in an npn or a pnp bipolar junction transistor (BJT).
However, in ESD protection, it is necessary that any thermal energy generated in the device is quickly dissipated so that the functionality of the ESD device is not reduced due to any build up of thermal energy. In the device disclosed in U.S. Pat. No. 7,700,449, there is no direct path to allow the dissipation of thermal energy generated when an ESD occurs.